4 ms·
> It doesn't matter how much IP secret sauce Xilinx or Altera have in their fabric, every single team out there hates the locked in toolchain and is slowed down
by tn1 6y ago
> It doesn't matter how much IP secret sauce Xilinx or Altera have in their fabric, every single team out there hates the locked in toolchain and is slowed down by it in a non-negligible way.
Unfortunately this isn't really a compelling reason to switch for most shops. The choice of FPGA is entirely driven by the features of the parts that the vendor offers. Salespeople talk to the relevant engineers and a part + pricing is negotiated accordingly.
Once you start pushing the limits of what your part can do, your design necessarily becomes tied to the details of the chip. The secret sauce is the reason why a specific part is bought!
At least Vivado (on Linux) is actually quite painless once you get the hang of it. If you're an important enough customer, you can complain to your FAE and they'll get you access to unreleased versions with a specific problem fixed.
- DoingIsLearning 6y agoI have to agree with the comment from bsder, unless you are doing heavy-duty video, RADAR, or RF comms the large majority of chips are never fully utilized, these business are really quite dependent on sales pitches/push. For the large majority of clients they just need to implement a small/medium time critical task. > At least Vivado (on Linux) is actually quite painless once you get the hang of it. If you're an important enough customer, you can complain to your FAE and they'll get you access to unreleased versions with a specific problem fixed. I disagree, I haven't touched Vivado in about 1 year but I doubt it revolutionized itself in 2020.X . I am going to politely ignore the shear volume of files that get auto-generated, duplicated, cached etc. and make it near impossible to version control. I also won't enumerate the GUI bugs that are only resolved with TCL scripting. However, as of 2019, Vivado was still unable to support VHDL-2008 standard simulations, same thing for packaging IP in VHDL-2008, that is literally 11 years behind in VHDL standard support. In any other industry people would be flipping the table. The problem is they don't make money out of the software they make money selling chips, and that is the wrong incentive to improve the toolchain. I would much rather they charge for the toolchain but actually support it with adequate resources and a sane development roadmap, OR they just accept the lack of budget, capacity, profit in software and open-source it.