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Do these chips have JTAG or BIST? can the chip itself tell you that the analog VDD is too high? Do you think these problems are specific to the dev board or an
by seg_lol 6y ago
Do these chips have JTAG or BIST? can the chip itself tell you that the analog VDD is too high?
Do you think these problems are specific to the dev board or an issue with the ECP5 itself?
I have glanced at these parts, but when I saw the -5G, I almost completely ignored the non -5G variant. The high speed serdes is just too attractive.
Is there something besides cost that you went with the non-5G parts?
- jhallenworld 6y agoIt's a combination of cost and the fact that Lattice's SGMII PCS IP does not support ECP5-5G, only ECP5 (you find this out by trying to instantiate it with "Clarity Designer"). It makes me wonder if the ECP5-5G SERDES supports 1 G Ethernet.. the datasheet claims that it does.. https://www.latticesemi.com/en/Products/DesignSoftwareAndIP/IntellectualProperty/IPCore/IPCores01/SGMIIGbEthernetPCS https://www.latticesemi.com/en/Products/DesignSoftwareAndIP/... Most people would use a separate PHY chip for Gigabit Ethernet, but we are in a space constrained design and wanted to avoid it (it's a custom camera). Actually, I could not get Lattice's SGMII PCS IP to work, so I ended up writing my own (I also wrote the MAC, IP and UDP layers- avoiding all for-pay IP for this project, so in fact I could use the open-source tool chain). I should try it on the ECP5-5G dev. board... I think I will do that.. We see the issue on both the ECP5 Versa card and our own custom card.
- seg_lol 6y agoThat sucks. I'd bite the bullet at this point and use an external phy if you can, at least carve out some board space for it and have it as a backup plan. > I ended up writing my own (I also wrote the MAC, IP and UDP layers lol. of course you did. @jhallenworld also created an OSH relay computer. :) You really should present at orconf or latchup!