3 ms·

Is this the board you are using? https://www.latticesemi.com/products/developmentboardsandkits/ecp5versadevelopmentkit https://www.latticesemi.com/products/dev

Is this the board you are using? https://www.latticesemi.com/products/developmentboardsandkits/ecp5versadevelopmentkit https://www.latticesemi.com/products/developmentboardsandkit... Lattice eng support is probably your best bet.

jhallenworld 6y ago
Yes. One hint for anyone who tries this: The voltage is wrong. The same board is used for ECP5 and ECP5-5G, but the analog VDD is set for the ECP5-5G chip, which is too high for ECP5 non-5G. With too high analog VDD, the SERDES TX PLL does not lock at lower frequencies (and the TXPLL loss of lock indicator is set). (Also this board has a 156.56 MHz oscillator, but you really need a 125 MHz clock for Ethernet. I just replaced the oscillator with a 125 MHz one, but other solutions are probably acceptable). Even with this fix, and after you connect it to the network, the SERDES comma detect indication is sometimes stable after power up, and sometimes not. Resetting the SERDES does not help. The register interface to the SERDES allows you to repower the TXPLL. So right now, my RISC-V softcore repowers it every second until the first link up happens. After the first successful link-up, it's fine. This hack does not work on every board, unfortunately. Yes, I've contacted Lattice support, no response from them in a long time. ECP5 is pretty dated at this point, so I'm wondering if any of the development team is left to support it.
- seg_lol 6y ago
  Do these chips have JTAG or BIST? can the chip itself tell you that the analog VDD is too high? Do you think these problems are specific to the dev board or an issue with the ECP5 itself? I have glanced at these parts, but when I saw the -5G, I almost completely ignored the non -5G variant. The high speed serdes is just too attractive. Is there something besides cost that you went with the non-5G parts?
  - jhallenworld 6y ago
    It's a combination of cost and the fact that Lattice's SGMII PCS IP does not support ECP5-5G, only ECP5 (you find this out by trying to instantiate it with "Clarity Designer"). It makes me wonder if the ECP5-5G SERDES supports 1 G Ethernet.. the datasheet claims that it does.. https://www.latticesemi.com/en/Products/DesignSoftwareAndIP/IntellectualProperty/IPCore/IPCores01/SGMIIGbEthernetPCS https://www.latticesemi.com/en/Products/DesignSoftwareAndIP/... Most people would use a separate PHY chip for Gigabit Ethernet, but we are in a space constrained design and wanted to avoid it (it's a custom camera). Actually, I could not get Lattice's SGMII PCS IP to work, so I ended up writing my own (I also wrote the MAC, IP and UDP layers- avoiding all for-pay IP for this project, so in fact I could use the open-source tool chain). I should try it on the ECP5-5G dev. board... I think I will do that.. We see the issue on both the ECP5 Versa card and our own custom card.
    - seg_lol 6y ago
      That sucks. I'd bite the bullet at this point and use an external phy if you can, at least carve out some board space for it and have it as a backup plan. > I ended up writing my own (I also wrote the MAC, IP and UDP layers lol. of course you did. @jhallenworld also created an OSH relay computer. :) You really should present at orconf or latchup!
- Teknoman117 6y ago
  > Yes, I've contacted Lattice support, no response from them in a long time. ECP5 is pretty dated at this point, so I'm wondering if any of the development team is left to support it. I wonder what the remaining life of the ECP5-5G is then. It would be really cool to have PCIe support on one of the reverse engineered FPGAs. I suppose project x-ray (Xilinx Series 7 reverse engineering) is coming along nicely, but at least ECP5 support is complete, even if everything about the SERDES isn't quite stable yet. As far as designing a board goes, it's a bit hard to choose. While the Lattice parts with PCIe are close to being made to work with open tools, the official Lattice development tools for the parts with SERDES have no free tier (beyond the 1 year license you get by purchasing that versa board), whereas everything in the Xilinx Artix-7 series for instance supports the free tier WEBPACK tools.
  - jhallenworld 6y ago
    You get the 1 year license even with the $99 ECP5-5G evaluation board, so not a very big deal.. just keep buying boards until the open source stuff is complete. Lattice parts are cheaper, so better for your profit margin. Lattice chips are available in some smaller packages if that matters to you. Diamond is OK, but I would not trust it with very full or aggressive designs, Vivado and Quartus are better. On the other hand, Lattice uses Synopsis Synplify for synthesis, which is very good.

jhallenworld 6y ago

Yes. One hint for anyone who tries this: The voltage is wrong. The same board is used for ECP5 and ECP5-5G, but the analog VDD is set for the ECP5-5G chip, which is too high for ECP5 non-5G. With too high analog VDD, the SERDES TX PLL does not lock at lower frequencies (and the TXPLL loss of lock indicator is set). (Also this board has a 156.56 MHz oscillator, but you really need a 125 MHz clock for Ethernet. I just replaced the oscillator with a 125 MHz one, but other solutions are probably acceptable). Even with this fix, and after you connect it to the network, the SERDES comma detect indication is sometimes stable after power up, and sometimes not. Resetting the SERDES does not help. The register interface to the SERDES allows you to repower the TXPLL. So right now, my RISC-V softcore repowers it every second until the first link up happens. After the first successful link-up, it's fine. This hack does not work on every board, unfortunately. Yes, I've contacted Lattice support, no response from them in a long time. ECP5 is pretty dated at this point, so I'm wondering if any of the development team is left to support it.

seg_lol 6y ago
Do these chips have JTAG or BIST? can the chip itself tell you that the analog VDD is too high? Do you think these problems are specific to the dev board or an issue with the ECP5 itself? I have glanced at these parts, but when I saw the -5G, I almost completely ignored the non -5G variant. The high speed serdes is just too attractive. Is there something besides cost that you went with the non-5G parts?
- jhallenworld 6y ago
  It's a combination of cost and the fact that Lattice's SGMII PCS IP does not support ECP5-5G, only ECP5 (you find this out by trying to instantiate it with "Clarity Designer"). It makes me wonder if the ECP5-5G SERDES supports 1 G Ethernet.. the datasheet claims that it does.. https://www.latticesemi.com/en/Products/DesignSoftwareAndIP/IntellectualProperty/IPCore/IPCores01/SGMIIGbEthernetPCS https://www.latticesemi.com/en/Products/DesignSoftwareAndIP/... Most people would use a separate PHY chip for Gigabit Ethernet, but we are in a space constrained design and wanted to avoid it (it's a custom camera). Actually, I could not get Lattice's SGMII PCS IP to work, so I ended up writing my own (I also wrote the MAC, IP and UDP layers- avoiding all for-pay IP for this project, so in fact I could use the open-source tool chain). I should try it on the ECP5-5G dev. board... I think I will do that.. We see the issue on both the ECP5 Versa card and our own custom card.
  - seg_lol 6y ago
    That sucks. I'd bite the bullet at this point and use an external phy if you can, at least carve out some board space for it and have it as a backup plan. > I ended up writing my own (I also wrote the MAC, IP and UDP layers lol. of course you did. @jhallenworld also created an OSH relay computer. :) You really should present at orconf or latchup!
Teknoman117 6y ago
> Yes, I've contacted Lattice support, no response from them in a long time. ECP5 is pretty dated at this point, so I'm wondering if any of the development team is left to support it. I wonder what the remaining life of the ECP5-5G is then. It would be really cool to have PCIe support on one of the reverse engineered FPGAs. I suppose project x-ray (Xilinx Series 7 reverse engineering) is coming along nicely, but at least ECP5 support is complete, even if everything about the SERDES isn't quite stable yet. As far as designing a board goes, it's a bit hard to choose. While the Lattice parts with PCIe are close to being made to work with open tools, the official Lattice development tools for the parts with SERDES have no free tier (beyond the 1 year license you get by purchasing that versa board), whereas everything in the Xilinx Artix-7 series for instance supports the free tier WEBPACK tools.
- jhallenworld 6y ago
  You get the 1 year license even with the $99 ECP5-5G evaluation board, so not a very big deal.. just keep buying boards until the open source stuff is complete. Lattice parts are cheaper, so better for your profit margin. Lattice chips are available in some smaller packages if that matters to you. Diamond is OK, but I would not trust it with very full or aggressive designs, Vivado and Quartus are better. On the other hand, Lattice uses Synopsis Synplify for synthesis, which is very good.