That’s not true. RISC-V targets the full spectrum of processors (well, not 8/16-bit, so not the very low end). Some of the decisions they made, compared to say

That’s not true. RISC-V targets the full spectrum of processors (well, not 8/16-bit, so not the very low end). Some of the decisions they made, compared to say OpenRISC is made just to make the ISA easier to implement with superscalar CPUs (not having branch delay slots)