3 ms·
Actually it's unlikely that this 4-input adder is in a general purpose ALU, usually they're directly in the cache access path (there are games you can apply to
by Taniwha 6y ago
Actually it's unlikely that this 4-input adder is in a general purpose ALU, usually they're directly in the cache access path (there are games you can apply to cache and TLB accesses if the low bits of that adder come out early), or in a separate addressing ALU which adds an extra clock to a load or store
- ithkuil 6y agoI assume they still count towards defining the shortest possible pipeline stage duration
- Taniwha 6y agoIt depends on how you split it up of course, but there's another cost, if you pipeline the address calculation you effectively make the cpu's pipe longer and more importantly increase the cost of a mispredicted branch - which is where we're all spending our time trying to mitigate these days