4 ms·

> having to fuse super complex (5 instruction or more) sequences Can you give an example of someone advocating for 5 instruction fusion? Normally it's limited

> having to fuse super complex (5 instruction or more) sequences Can you give an example of someone advocating for 5 instruction fusion? Normally it's limited to three.

pizlonator 6y ago
I’d have to reinvestigate more than I feel like doing right now so I’ll tell you where to look. You need fast sequences for all of these variants: - add or sub or mul - signed or unsigned - 32 bit or 64 bit Some of those need 5 instructions. I don’t remember which adventure you need to pick to get 5.
- Veedrac 6y ago
  Thanks for the reply but I'm not sure what you mean. Are you saying you want to add an i32 to a u64? Or am I completely misunderstanding? I'm not sure why unsigned-unsigned or signed-signed instructions would be hard. Idk about mixed sign operations, but when do they ever occur without first casting one to the other?
  - pizlonator 6y ago
    I mean you will do overflow checks on the following. I’ll use the “s” and “u” prefixes to mean signed and unsigned. Unsigned matters less than signed. sadd32, sadd64, uadd32, uadd64, ssub32, ssub64, usub32, usub64, smul32, smul64, umul32, umul64
    - Veedrac 6y ago
      Ah, I get you now. Yes, this looks like a weak point, and I totally get why it'd screw with Javascript optimizations. I don't think it's a fusion problem; even if you did fuse these sequences, they'd still be bad, since they'd be writing lots of extra registers.
      - pizlonator 6y ago
        Yeah exactly! And worth noting that these are just the ones where you usually have good sequences on other cpus, but even then (like signed mul) they’re not perfect. Lots of room for improvement. It’s just that risc-v didn’t seize the opportunity.
brandmeyer 6y ago
rotate-and-xor (and xor-and-rotate) are both common operations in ARX ciphers. They demand 4 macro-ops in RISC-V, but only one in ARMv8. Bitfield insertion is only one instruction in most RISC ISAs, but 5 or more in RISC-V.
- Veedrac 6y ago
  The (unfinalized) bitmanip extension has single-op rotates.
  - CalChris 6y ago
    I really don't like it. It seems like they copied x86 (bext, bdep) where they should have been plagiarizing armv8 (BFM, ...).
    - brandmeyer 6y ago
      I've watched that extension's development since it was little more than one smart guy's wish list. I don't think its fair to say that they copied any one architecture. The authors have put in a ton of time researching the tradeoffs and investigating the trade space over the years. That said, until it gets ratified by the consortium and implemented in silicon its still just a (well-researched) wishlist.
jhallenworld 6y ago
They have this example for general signed overflow checking in the 2.2 spec (but I'm not sure if this counts as a recommended sequence for fusion): add t0, t1, t2 slti t3, t2, 0 slt t4, t0, t1 bne t3, t4, overflow So two extra registers needed also.. edit: so I now think a good extension to add overflow checking to RISC-V is with an instruction that works like "slt"- call it "sov", set if add would overflow: add t0, t1, t2 sov t3, t1, t2 bnez t3, overflow add/sov could be fused..
- Veedrac 6y ago
  Fusing that would be very difficult, since it's hard to write that many registers with a single op, and I don't think they recommend it. This does mean signed overflow checking will be comparatively expensive. But thanks for the reference, I agree this is a weak point :).
  - ithkuil 6y ago
    You don't have to use real registers in a single op. Fusing means interpreting a pattern in the input stream and issuing a different instruction from a richer microarchitectural instruction set
    - jcranmer 6y ago
      You have to preserve the architectural registers at the end of the sequence. So if there are 5 registers, you either have to have a 5-register microinstruction, or issue multiple 3-register microinstructions instead.
      - ithkuil 6y ago
        You have to preserve architectural registers only when some other instruction actually depends on them. When you detect a dependency you lazily compute their content (causing a stall)
        6y ago

> having to fuse super complex (5 instruction or more) sequences Can you give an example of someone advocating for 5 instruction fusion? Normally it's limited to three.

pizlonator 6y ago

I’d have to reinvestigate more than I feel like doing right now so I’ll tell you where to look. You need fast sequences for all of these variants: - add or sub or mul - signed or unsigned - 32 bit or 64 bit Some of those need 5 instructions. I don’t remember which adventure you need to pick to get 5.

Veedrac 6y ago
Thanks for the reply but I'm not sure what you mean. Are you saying you want to add an i32 to a u64? Or am I completely misunderstanding? I'm not sure why unsigned-unsigned or signed-signed instructions would be hard. Idk about mixed sign operations, but when do they ever occur without first casting one to the other?
- pizlonator 6y ago
  I mean you will do overflow checks on the following. I’ll use the “s” and “u” prefixes to mean signed and unsigned. Unsigned matters less than signed. sadd32, sadd64, uadd32, uadd64, ssub32, ssub64, usub32, usub64, smul32, smul64, umul32, umul64
  - Veedrac 6y ago
    Ah, I get you now. Yes, this looks like a weak point, and I totally get why it'd screw with Javascript optimizations. I don't think it's a fusion problem; even if you did fuse these sequences, they'd still be bad, since they'd be writing lots of extra registers.
    - pizlonator 6y ago
      Yeah exactly! And worth noting that these are just the ones where you usually have good sequences on other cpus, but even then (like signed mul) they’re not perfect. Lots of room for improvement. It’s just that risc-v didn’t seize the opportunity.

brandmeyer 6y ago

rotate-and-xor (and xor-and-rotate) are both common operations in ARX ciphers. They demand 4 macro-ops in RISC-V, but only one in ARMv8. Bitfield insertion is only one instruction in most RISC ISAs, but 5 or more in RISC-V.

Veedrac 6y ago
The (unfinalized) bitmanip extension has single-op rotates.
- CalChris 6y ago
  I really don't like it. It seems like they copied x86 (bext, bdep) where they should have been plagiarizing armv8 (BFM, ...).
  - brandmeyer 6y ago
    I've watched that extension's development since it was little more than one smart guy's wish list. I don't think its fair to say that they copied any one architecture. The authors have put in a ton of time researching the tradeoffs and investigating the trade space over the years. That said, until it gets ratified by the consortium and implemented in silicon its still just a (well-researched) wishlist.

jhallenworld 6y ago

They have this example for general signed overflow checking in the 2.2 spec (but I'm not sure if this counts as a recommended sequence for fusion): add t0, t1, t2 slti t3, t2, 0 slt t4, t0, t1 bne t3, t4, overflow So two extra registers needed also.. edit: so I now think a good extension to add overflow checking to RISC-V is with an instruction that works like "slt"- call it "sov", set if add would overflow: add t0, t1, t2 sov t3, t1, t2 bnez t3, overflow add/sov could be fused..

Veedrac 6y ago
Fusing that would be very difficult, since it's hard to write that many registers with a single op, and I don't think they recommend it. This does mean signed overflow checking will be comparatively expensive. But thanks for the reference, I agree this is a weak point :).
- ithkuil 6y ago
  You don't have to use real registers in a single op. Fusing means interpreting a pattern in the input stream and issuing a different instruction from a richer microarchitectural instruction set
  - jcranmer 6y ago
    You have to preserve the architectural registers at the end of the sequence. So if there are 5 registers, you either have to have a 5-register microinstruction, or issue multiple 3-register microinstructions instead.
    - ithkuil 6y ago
      You have to preserve architectural registers only when some other instruction actually depends on them. When you detect a dependency you lazily compute their content (causing a stall)
      - 6y ago