3 ms·
You need the icache to be post-fusion..
by jhallenworld 6y ago
You need the icache to be post-fusion..
- bertr4nd 6y agoIt’s not just the I$ though, it’s the MLC, LLC, and I-TLB. And instruction density at those levels actually matters quite a lot for big binaries (my experience in this regard is with HHVM at FB, but it’s certainly not unique).
- jhallenworld 6y agoYeah, pretty much agreeing with you. I think if they are going to rely on fusion in the ISA, they should limit it to the most minimal fusion implementation to have the widest possible chance of adoption. So assume the hardware can only fuse two instructions and design the ISA with this restriction in mind.
- brandmeyer 6y agoIntel and AMD's experience with complex transformations on the instruction stream suggests that its overall better to do it in a L0 decode cache.