3 ms·
The best design is control bits which RISC-V doesn’t have but x86 and ARM do have. The best design is part of the core ISA and not and extension since overflow
by pizlonator 6y ago
The best design is control bits which RISC-V doesn’t have but x86 and ARM do have.
The best design is part of the core ISA and not and extension since overflow checking is fundamental to modern languages.
- rwmj 6y agoYou need to either write a paper about this or produce some evidence.
- pizlonator 6y agoI don’t need to do anything. You’re welcome not to take my advice. :-) If you doubt that dynamic languages are using overflow checking in the way that I describe then it’s not because of lack of papers on the subject.
- wbl 6y agoControl bits as in ARM and x86 force serialization of arithmetic due to the RW dependency in every instruction on that bit. There are some tricks but it still needs tracking. For higher order superscalar or out of order processors this gets annoying.
- pizlonator 6y agoI think what you’re saying is basically true but it’s a trade against density. If you did overflow checks rarely then what you say is a very good point indeed. The key thing is just the frequency of this stuff in modern languages.
- deleted 6y ago[deleted]
- tom_mellior 6y agoARM has separate instruction variants with and without setting of flags. Normally one uses the flag-less versions, so you don't have this problem.
- CalChris 6y agoNo. Control bits (status bits, flags, ...) get renamed just as registers get renamed. Basically, if there's a bottleneck to x86 code, Intel has run into it, profiled for it and generally optimized around it both in their microarchitectures and in the their C compiler.
- wbl 6y agoThat's one of the tricks. But it doesn't solve the issue of clobbers, which Intel had to introduce new variants of ADD and MUL to solve. Named predicate registers make it all much easier for everyone.
- ansible 6y agoYes, the old, old way of having a single condition code register or the like (which dates back 40+ years) doesn't work well these days. I like the Mill CPU approach, where every "register" (it doesn't have named registers actually) has the full set of status bits associated with it, and not just for overflow. Things like "not a result" (NaR), which can represent the result of a failed speculative load for example (because the process doesn't have permission to read from that page, for example).
- saagarjha 6y agoI thought that compilers couldn't really use this effectively…
- ansible 6y ago> I thought that compilers couldn't really use this effectively… The status bits part in general, or the speculative load stuff? They allegedly have all this working, privately. They haven't released any development tools or such to the public. I've often toyed with the idea of writing an instruction-level simulator (as opposed to the RTL sim or whatever they have internally). But even sticking to the public information, I'd likely be infringing on their patents.
- CalChris 6y agoAgreed. Waterman's thesis says this about that: "Several ISA features, including implicit condition codes and predicated moves, are onerous to implement in aggressive microarchitectures. Yet, their complexity often does not result in higher performance because their semantics were ill-conceived. For example, x86 provides a conditional load instruction, but, if the unconditional load were to cause an exception, it is implementation-defined whether the conditional version would do so. Thus, a compiler can only rarely use this instruction to perform the if-conversion optimization. Recognizing the inefficiency of their conditional operations, Intel’s recent implementations go to some lengths to fuse comparison instructions and branch instructions into internal compare-and-branch operations." Yeah, doing condition codes right is complicated but then that's the purpose of microarchitecture, to factor that complexity out. RISC-V succeeds in having a minimalist to a fault design which is appropriate for a certain design point. ARMv8 and x86_64 are more useful for a broader set of designs. The burden now is on RISC-V to show that their minimalist approach is fast+efficient rather than just simple. You have to get something out of the simplicity; otherwise what you get is design debt.