> Essentially that's part of the whole RISC idea - simple means faster The problem with this is that today, your clock speed is bound by neither your decode no

> Essentially that's part of the whole RISC idea - simple means faster The problem with this is that today, your clock speed is bound by neither your decode nor your ALUs. Only implementing weaker ALUs makes sense from an optimization standpoint if it buys you more clock speed. But as it doesn't, it just leaves you competing with another CPU that has the same clock speed as you do, and which does a lot more per clock than you do.