6 ms·
The worst issue, at least for the versions of the ISA that will run a "real" OS, are the lack of conditional move instructions and lack of bitwise rotation inst
by bonzini 6y ago
The worst issue, at least for the versions of the ISA that will run a "real" OS, are the lack of conditional move instructions and lack of bitwise rotation instructions. Lack of shift-and-sum instructions or equivalently addresses with shifted indexes is usually mitigated by optimization of induction variables in the compiler. They are nice to have (I have written code where I took advantage of x86's ability to compute a+b*9 with a single instruction) but not particularly common with the massive inlining that is common in C++ or Rust.
The ugly parts are indeed all ugly, though they have now added hint instructions.
- saagarjha 6y agoYeah, IDK about the RISC ISAs–they seem to be designed around being architecturally simple (and I guess easy to teach?) but they really don't seem to map back to actual code at all, nor do they seem particularly grounded in hardware design either. (Or sometimes they're too close to the hardware and burn themselves…)
- d33 6y agoCould it be because of some patents that made it impossible to do it properly?
- nickik 6y agoNo. The just don't share the opinions. RISC-V is designed to go from the smallest possible core to high performance compute. Bit instructions will be in the 'B' extension.
- bumblebritches5 6y agoUmm, Unicode decoding/encoding REQUIRES bitwise operators to work... Not including that in the core ISA is a monumental mistake.
- ThrowawayR2 6y agoBitwise rotation instructions date back to at least the PDP-8. Even if they were patentable, the patents would have expired long ago.
- varispeed 6y agoCan you not add these instructions? At least when you use FPGA IP, it can be done. But you would have to update the toolchain etc to support these new instructions.
- Veedrac 6y agoThey have added them, it's just they're in bitmanip, which isn't finalized, nor is the extension mandatory.
- fulafel 6y agoHave decent speedups been gotten by previous CPUs by the addition of conditional moves? IIRC for some the SPECcpu impact was negligible, amd many RISCs don't have it. RISC is about quantifying this kind of thing and skipping marginal additions after all.
- PeCaN 6y agoI'm not sure about this "RISC way" stuff. From a uarch standpoint the RISC vs CISC distinction is moot and from an ISA standpoint the only real quantifiable difference seems to be being a load-store architecture. ISAs without conditional moves tend to have predicated instructions which are functionally the same thing. I'm not actually aware of any traditionally RISC architectures that have neither conditional moves or predicated instructions. While ARMv7 removed predicated instructions as a general feature ARMv8 gained a few "conditional data processing" instructions (e.g. CSEL is basically cmov), so clearly at least ARM thinks there's a benefit even with modern branch predictors. Conditional instructions are really, really handy when you need them. It's an escape hatch for when you have an unbiased branch and need to turn control flow into data flow.
- fulafel 6y agoWe were talking ISAs so let's focus on that. The quantifiability comes from measuring results when you give compilers new instructions, vs paying implementation complexity (time, money and future baggage to support the insn forever). The upsides and downsides here come in different units so it's still tricky. Lots of instructions can be proposed with impressive qualitative speeches convincing you how dandy they are, but in the end it's down to the real world speedup yield vs the price you pay in complexity and resulting second order effects. (In rarer cases the instructions might be added not for performance reasons but to ease complexity and cost, that's where qualitative arguments still have a place when arguing for adding instructions). It's fine if we don't have the evidence in this thread - I was just asking on the off chance that someone can point to a reference.
- PeCaN 6y ago
- tralarpa 6y agoI thought the scale factor is either 1,2,4 or 8?
- saagarjha 6y agoYou can combine them. For example, [rax+rax*8+1] (base register, register shifted by 8, constant).
- tralarpa 6y agoIsn't the scale factor encoded in just two bits? (i.e. 00=1, 01=2, 10=4, 11=8)
- saagarjha 6y agoJust edited with an example; I’m on my iPhone so assembling via nasm takes an extra minute ;)
- tralarpa 6y agoThanks for the example. I was assuming that a and b are variables in OPs posting.
- bonzini 6y agoTrue that. In my case it was 12+x*9, which is log2 of the page sizes on x86 (4K, 2M, 1G).
- vardump 6y ago> I have written code where I took advantage of x86's ability to compute a+b*9 with a single instruction... Didn't check, but I suspect that decodes at least into two microinstructions.
- pizlonator 6y agoI’m assuming a is a constant in your example and that you’re doing a(b, b, 8). That’s one cycle on modern intels I believe (I think the manual promised this for Nehalam). OP also alludes right this fact when talking about fusion.
- pbsd 6y agoNot only is it a single uop for the last 10 years of Intel chips, you can also run 2 of them per cycle.
- bumblebritches5 6y agoNope. It's a pretty famous instruction, FMA Fused Multiply-Add