The bits are in a matrix, with sense lines in silicon vertically and row select lines in metal horizontally. When a row select line is activated, 128 transistor

The bits are in a matrix, with sense lines in silicon vertically and row select lines in metal horizontally. When a row select line is activated, 128 transistors are turned on and each sense line is connected to the single capacitor in that row. Thus, 128 bits are read in parallel. Thus, each horizontal row select line is connected to 128 different transistor gates, in other words connected to 64 of the diagonal poly 2 regions. The confusing part is that the rows zig-zag a bit to improve the density. In other words, the physical rows in the photo don't quite match the electrical/logical rows. Look at the photo and imagine pulling it apart like a zipper. Then shift the middle part up half a step so the capacitors line up. Then the logical rows are all in a straight line. Hopefully that explanation isn't entirely confusing. In brief, the two capacitors with the same poly 2 diagonal are in the same electrical row, so they are selected together (along with 126 other capacitors). I'll probably write more about this, so let me know if there is a clearer way to explain this :-)