It's been used since 2018 for smaller, power optimized designs. This would be the first significant high performance design, and at comparatively huge die sizes

It's been used since 2018 for smaller, power optimized designs. This would be the first significant high performance design, and at comparatively huge die sizes. Also claimed the process was semi-custom for nvidia, not the "standard" 8nm. Unclear what exactly was different, though, but depending on the changes (if any) it may actually not be yielding as well as a 2 year old process should