A long time ago when I was writing Verilog and VHDL what people were doing beyond the 1Bn gate (I still keep using gates rather than transistors as a unit, funn

A long time ago when I was writing Verilog and VHDL what people were doing beyond the 1Bn gate (I still keep using gates rather than transistors as a unit, funny) scale were statistical sampling methods to try to uncover certain stuck / flakey gates so certain more risky or critical paths were tested a bit better. Then there's also error correction mechanisms that are more common nowadays that can compensate to some extent. We don't test for every single possible combinatoric like was possible so long ago, full stop. Furthermore, GPUs aren't necessarily to be tested in the same ways as CPUs. GPUs don't really branch and hold state with exotic addressing modes like how CPUs can operate, so testing compute shaders is in many respects closer to testing not a state machine as much as a big, wide bit bus. Heck, one doesn't need to even bother hooking up any output devices like HDMI and HDCP decoders to a GPU as long as the PCB is hooked up fine during assembly and the peripheral chips are tested to spec, too. And for an extra measure of automation there are test suites that are programmed into hardware that can drive chips at line speed on a test bench.