> It can be noted that the cell size reduction rate from 2017 to 2018 to 2019 is much slower than the rate for preceding years 2011 to 2017, showing that SRAM c

> It can be noted that the cell size reduction rate from 2017 to 2018 to 2019 is much slower than the rate for preceding years 2011 to 2017, showing that SRAM cells have not been scaling at the same rate as logic in general. At IEDM 2019, the 5nm process was quoted to have 1.84x logic density improvement compared to 1.35x SRAM density improvement[1] 0.021um per cell [1] for TSMC N5 vs 0.027um per cell [0] for TSMC N7. Even if Apple did everything right, they'd still be behind due to the limits of the process. [0]https://fuse.wikichip.org/news/2408/tsmc-7nm-hd-and-hp-cells-2nd-gen-7nm-and-the-snapdragon-855-dtco/ https://fuse.wikichip.org/news/2408/tsmc-7nm-hd-and-hp-cells... [1]https://semiwiki.com/semiconductor-manufacturers/tsmc/283487-tsmcs-5nm-0-021um2-sram-cell-using-euv-and-high-mobility-channel-with-write-assist-at-isscc2020/ https://semiwiki.com/semiconductor-manufacturers/tsmc/283487...