4 ms·
Conway CPU in Hardware Memory?
It is possible to create a general purpose, Turing
complete computer using Conway's rules:
https://news.ycombinator.com/item?id=24831268
Is anyone aware of what hardware circuits would be required if you wanted to create this in hardware memory? What does a single "Conway memory cell" circuit look like?
It should be possible to implement this circuit on an FPGA.
In addition, rather than loading the FPGA with a general purpose "Conway CPU", one could optimize it for the particular problem (e.g. matrix multiplies).
It seems to me that implementing the CPU "in the memory" would overcome the "memory wall" problem (moving data between the CPU and memory).
- PaulHoule 6y agoIn terms of physics I think the Game-of-Life computer has the same scaling problem. If a computer is built in a plane and you draw a line cutting it in half, the bandwidth across the line is going to be proportional to the length of the line (L). If the system as a whole is round, the area is proportional to L^2. If the computer had a scalable 3-d structure then you would have the same problem with a bisecting plane (L^2) and the volume (L^3). If you give up the assumption that an arbitrary half of the computer should be able to use the full bandwidth to talk to the other half, you can do better. For instance, that "2-d" computer could be built in a 2 tiles x N tiles direction and the aggregate transfer of data between row 1 and row 2 scales as N increases, but in the other direction it does not scale at all.
- eesmith 6y agoThe direct implementation of the Life system could be implemented as a bit per cell, along with a few dozen gates and timing circuitry. However, have you ever seen the systems used to emulate logic circuits? They take a lot of cells. Eg, https://nicholas.carlini.com/writing/2020/intro-to-circuits-game-of-life.html https://nicholas.carlini.com/writing/2020/intro-to-circuits-... . You end up using scores of cells to emulate one simple logic circuit - and the implementation contains many hardware versions of that logic circuits. Note also that in practice the high-performance, long-time Life implementations use hashlife. This gets its speedup because of redundancies in large life boards - a redundancy that doesn't really exist for, say, matrix multiplies. And hashlife is harder to implement in hardware.