3 ms·
I’m pretty sure x86 does have split L1i and L1d. From Wikipedia (not the best source I know): “L1 cache size unchanged at 32 KB (KiB) instruction and 32 KB (K
by senkora 6y ago
I’m pretty sure x86 does have split L1i and L1d.
From Wikipedia (not the best source I know):
“L1 cache size unchanged at 32 KB (KiB) instruction and 32 KB (KiB) data cache per core.“
https://en.m.wikipedia.org/wiki/Skylake_(microarchitecture) https://en.m.wikipedia.org/wiki/Skylake_(microarchitecture)