5 ms·

[ec2-user@ip-10-0-42-228 ~]$ lscpu ... L1d cache: 64K L1i cache: 64K L2 cache: 1024K L3 cache: 32768K Find

• wyldfire 6y ago
  Of course, you can't compare those directly with epyc/xeon because of the architectural/instruction set differences. EDIT: meaning that a larger sized cache wouldn't necessarily deliver better performance (though I think in this case the architectural differences do favor Graviton making better use of cache)
• darksaints 6y ago
  I couldn't find anything on the differences between the two different L1 caches. What's the purpose for a second L1 cache?
  • sitharus 6y ago
    The ARM architecture is a modified Harvard architecture, so the CPU has separate instruction and data L1 caches. x86 CPUs don't have this separation.
    • senkora 6y ago
      I’m pretty sure x86 does have split L1i and L1d. From Wikipedia (not the best source I know): “L1 cache size unchanged at 32 KB (KiB) instruction and 32 KB (KiB) data cache per core.“ https://en.m.wikipedia.org/wiki/Skylake_(microarchitecture) https://en.m.wikipedia.org/wiki/Skylake_(microarchitecture)
    • lights0123 6y ago
      $ lscpu Architecture: x86_64 Model name: AMD Ryzen 7 2700X Eight-Core Processor L1d cache: 256 KiB L1i cache: 512 KiB L2 cache: 4 MiB L3 cache: 16 MiB