That chip was nothing but a PowerPC Risc with some special functions. Nothing too exting. If you really want to tackle Lattice QCD with ASICS you could go much

That chip was nothing but a PowerPC Risc with some special functions. Nothing too exting. If you really want to tackle Lattice QCD with ASICS you could go much further than this chip. Since Lattice QCD is nothing more than Monte Carlo integration over a specific Hamiltonian you could start with implementing a good deterministic random number generator in hardware. Then you can make some major optimizations calculating the Hamiltonian by cleverly seperating addition and multiplication and trasformation to a logarithmic number system, so that you only have additions in the end. All of this has already been implemented on a FPGA years ago.