> think fixed-instruction, l[...]. That's what RISC really means today. > No variable-length instructions. So, ARM is not a RISC instruction set, because T32

> think fixed-instruction, l[...]. That's what RISC really means today. > No variable-length instructions. So, ARM is not a RISC instruction set, because T32 (Thumb-2) instruction can be 2 or 4 bytes long. Similarly, RISC-V has variable-length instructions for extensibility. See p. 8ff of https://github.com/riscv/riscv-isa-manual/releases/download/Ratified-IMAFDQC/riscv-spec-20191213.pdf https://github.com/riscv/riscv-isa-manual/releases/download/... (section "Expanded Instruction-Length Encoding").