3 ms·
It writes an invalid instruction at this location. What ever this instruction, it just has to be invalid. RISC-V actually did this in a special instruction cal
by qlk1123 6y ago
It writes an invalid instruction at this location. What ever this instruction, it just has to be invalid.
RISC-V actually did this in a special instruction called ebreak. It can change the CPU privileged mode into Debug Mode.
- wazari972 6y agoAuthor here. As I mentioned above, I will rewrite this sentence to include dedicated special instructions. It was a wording mistake not to mention it!