When RISC first appeared they really were simpler than competing designs. But today I think it's hard to argue that modern pipelined, out of order processors w

When RISC first appeared they really were simpler than competing designs. But today I think it's hard to argue that modern pipelined, out of order processors with hundreds of millions of transistors are in any sense 'simple'. If there is a general lesson to be learned it's that the processor is often best placed to optimise on the fly rather than have the compiler try to do it (VLIW) or trying to fit a complex ISA to match the high level language you're running.