There are so many cool 801 stories (like why 801? The building it was designed in was number 801). My favorite feature was this: stack frames were cache align

There are so many cool 801 stories (like why 801? The building it was designed in was number 801). My favorite feature was this: stack frames were cache aligned and the line under the stack pointer would be marked valid upon entry of functions (so the storing the callee saves wouldn't bring in a line that would be overwritten anyway) and invalidated upon exit (so the cached wouldn't have to write back stale data). As he said, this effectively enabled them to treat the cache as an extended register file. Strangely nobody has copied this idea. There are great stories about the development, but very little other detail is available and AFAICT, very few were actually built. 801 was not a single chip design and RISC didn't become an overnight success until it was built in a single chip (which enabled much higher frequency and was the true key to success). ADDED: Also, their simulator had a neat trick to make it fast: all I$ lines had an 8X (IIRC) shadow where for each fetched instruction there would be a short sequence of host instructions emulating it. Thus to simulate an 801 instruction they would just ensure the line was fetched and branch directly to the corresponding address in the simulation cache which could fall through to the next instruction until either a branch or the end of the line was reached.