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> One can designate unaligned access as "undefined behavior" and leave it to compiler writers to make things right. Lots of hardware architectures have tried t

> One can designate unaligned access as "undefined behavior" and leave it to compiler writers to make things right. Lots of hardware architectures have tried to levy this requirement on the software. Every one has subsequently walked it back and provided unaligned access support in hardware. Even RISC-V, which is as orthodox a RISC as it gets, supports unaligned access in hardware. So that's got to be the baseline for deciding how much additional work must be performed when supporting something new: Any memory instruction may touch two pages, but the vast majority of them won't.

thesz 6y ago
MIPS has four (two instructions for loads and two for stores) instructions exactly for unaligned access situation, when it cannot be handled in software. This is exactly what I am talking about. BTW, MIPS were proud that their ISA is as good as microcode, and the solution with two instructions is exactly that - expose as much of abstract internals as possible. Thus, I cannot agree with you on "every hardware architecture walked back". https://en.wikipedia.org/wiki/Lexra https://en.wikipedia.org/wiki/Lexra - for an historical expose.
- brandmeyer 6y ago
  MIPS did in fact walk it back with MIPSr6 and nanoMIPS. The old unaligned-half-access instructions were dropped entirely, and most memory access instructions support unaligned access natively.
  - thesz 6y ago
    https://en.wikipedia.org/wiki/MIPS_architecture#MIPS32/MIPS64 https://en.wikipedia.org/wiki/MIPS_architecture#MIPS32/MIPS6... It contains "possibly via trapping" which I am not at all against of. What is interesting there that MIPS introduced BALIGN instruction which reminds me of first generation of Alpha ISA. Alpha did not had byte or word (16-bit) memory access. These should be provided using 32-bit word access and some shuffling. They walked back on that for code size reasons and later Alpha ISAs had byte and 16-bit loads and stores. I do not have reference ready but I believe they were aligned accesses.

thesz 6y ago

MIPS has four (two instructions for loads and two for stores) instructions exactly for unaligned access situation, when it cannot be handled in software. This is exactly what I am talking about. BTW, MIPS were proud that their ISA is as good as microcode, and the solution with two instructions is exactly that - expose as much of abstract internals as possible. Thus, I cannot agree with you on "every hardware architecture walked back". https://en.wikipedia.org/wiki/Lexra https://en.wikipedia.org/wiki/Lexra - for an historical expose.

brandmeyer 6y ago
MIPS did in fact walk it back with MIPSr6 and nanoMIPS. The old unaligned-half-access instructions were dropped entirely, and most memory access instructions support unaligned access natively.
- thesz 6y ago
  https://en.wikipedia.org/wiki/MIPS_architecture#MIPS32/MIPS64 https://en.wikipedia.org/wiki/MIPS_architecture#MIPS32/MIPS6... It contains "possibly via trapping" which I am not at all against of. What is interesting there that MIPS introduced BALIGN instruction which reminds me of first generation of Alpha ISA. Alpha did not had byte or word (16-bit) memory access. These should be provided using 32-bit word access and some shuffling. They walked back on that for code size reasons and later Alpha ISAs had byte and 16-bit loads and stores. I do not have reference ready but I believe they were aligned accesses.