There's a reason for that. Another errata for the same part explains that: > If an interrupt occurs during an CPU AHB burst read access to one SDRAM internal b

There's a reason for that. Another errata for the same part explains that: > If an interrupt occurs during an CPU AHB burst read access to one SDRAM internal bank followed by a second read to another SDRAM internal bank, it may result in wrong data read if all the conditions below are met: > • SDRAM read FIFO enabled. RBURST bit is set in the FMC_SDCR1 register > • An interrupt occurs while CPU is performing an AHB incrementing bursts read access of unspecified length (using LDM = Load Multiple instruction) to one SDRAM internal bank and followed by another CPU read access to another SDRAM internal bank.