5 ms·
Yes, this instruction was removed in 64-bit arm for this very reason. It has been replaced with LDP (load pair, i.e load two registers) which is not nearly as
by panpanna 6y ago
Yes, this instruction was removed in 64-bit arm for this very reason.
It has been replaced with LDP (load pair, i.e load two registers) which is not nearly as nice for software developers but made the life of the ARM designers much easier. For comparison:
https://elixir.bootlin.com/linux/v4.14.52/source/arch/arm64/kernel/entry.S#L308 https://elixir.bootlin.com/linux/v4.14.52/source/arch/arm64/...
https://elixir.bootlin.com/linux/v4.14.52/source/arch/arm/kernel/entry-armv.S#L167 https://elixir.bootlin.com/linux/v4.14.52/source/arch/arm/ke...
BUT, I don't think we will see real benefits of this unless we remove aarch32 support from ARMv8.
- gok 6y agoMany aarch64 chips have no aarch32 support for reasons like this
- repiret 6y agoMany? Arm Ltd designed Armv8-a chips fall into three tiers: • Support AArch32 at EL0-EL3 (everywhere) • Support AArch32 at EL0 (user mode) • No AArch32 support The most fielded cores fall into the first category. The newer cores - A76 and it’s contemporaries IIRC - fall into the second category. Only it’s recently disclosed data center cores fall into the third category.