13 ms·

So, 1 instruction, but how many clock cycles does it take to load 16 registers?

Someone 6y ago
Chances are high it depends on the CPU, whether the memory read/written straddles a cache line, etc. https://gab.wallawalla.edu/~curt.nelson/cptr380/textbook/advanced%20material/Appendix_B3.pdf https://gab.wallawalla.edu/~curt.nelson/cptr380/textbook/adv... says it takes 2 + N cycles, plus 2 if the PC is in the list. Storing them takes 1 + N cycles, according to that PDF. (Also, this kind of instruction isn’t a novel idea. 68k had MOVEM, for example (http://68k.hax.com/MOVEM http://68k.hax.com/MOVEM))
progval 6y ago
According to https://developer.arm.com/documentation/ddi0165/b/instruction-cycle-times/instruction-cycle-count-summary https://developer.arm.com/documentation/ddi0165/b/instructio... , it's 17 clock cycles if the next instruction uses the last register (r15), otherwise 16
- monocasa 6y ago
  If anyone is interested why R15 is special cased here a bit, it's because R15 is the program counter and that extra cycle is the interlock where they'd otherwise have to put a delay slot.
  - progval 6y ago
    Hmm, I didn't know about that. Then it would be 20 or something. (The special case I accounted for is because there's a bubble in the instruction pipeline if the next instruction uses the last register)
eximius 6y ago
Are instructions typically variable in the number of cycles it takes? If, as the article claims, pop is truly aliased to ldm, then I'd expect it to be very fast.
- progval 6y ago
  They are, this one takes from 2 to something like 20 cycles, depending on the number of registers, an whether the PC is one of them.
- lxgr 6y ago
  > Are instructions typically variable in the number of cycles it takes? Very much so, either due to memory latency or just inherent complexity. For example, a single division instruction can easily take the same time as ten adds.
  - eximius 6y ago
    I meant variant for the same instruction. Is expect a divide to be slower than an add but I wasn't sure if a single instruction would have a range.
- grandmczeb 6y ago
  Yes, even in very simple architectures instructions often take different numbers of cycles.
pja 6y ago
Who cares? Feel that code density ! More seriously, yup: if you read the architecture manual this instruction can take a long time. It's also a pain for a OoO (not superscalar!) cpu to keep track of all the dependencies. It made complete sense back in the early 80s when the instruction set was designed, but like universal condition code dependent instruction execution it was dropped from ARM64 for good reasons.
- monocasa 6y ago
  Superscalar doesn't really matter here (just throw in an interlock), but out of order very much does.
  - pja 6y ago
    True! I was (inappropriately) thinking of SS as a combination of both.
- kevincox 6y ago
  Why would it be harder for OoO to keep track of this than N mov/load instructions? It is just that the dependency tracker is working in instruction space? As mentioned before these were microcoded anyways so it may end up "compiling" down to N loads which should track just as well.
  - alain94040 6y ago
    Imagine you hit a bus error on the last memory access of LDM. You already updated 15 registers, so now you need to undo all of that. If instead you had executed 16 separate LD instructions, all of them would have retired and update state by the time the last one gets the bus error. It’s all doable of course, but it means your OOO algorithm and physical implementation need to handle a lot more state in flight.
    - tsomctl 6y ago
      Why couldn't you just not undo it, and have it read/write twice? This wouldn't be a problem if you're accessing normal ram, like the prologue and epilogue of a function. Add a comment to the manual saying to not use this instruction when reading/writing hardware registers where accessing it changes state.
LIV2 6y ago
Less than 16 individual loads since you're skipping 15 opcode fetches

Chances are high it depends on the CPU, whether the memory read/written straddles a cache line, etc. https://gab.wallawalla.edu/~curt.nelson/cptr380/textbook/advanced%20material/Appendix_B3.pdf https://gab.wallawalla.edu/~curt.nelson/cptr380/textbook/adv... says it takes 2 + N cycles, plus 2 if the PC is in the list. Storing them takes 1 + N cycles, according to that PDF. (Also, this kind of instruction isn’t a novel idea. 68k had MOVEM, for example (http://68k.hax.com/MOVEM http://68k.hax.com/MOVEM))

progval 6y ago

According to https://developer.arm.com/documentation/ddi0165/b/instruction-cycle-times/instruction-cycle-count-summary https://developer.arm.com/documentation/ddi0165/b/instructio... , it's 17 clock cycles if the next instruction uses the last register (r15), otherwise 16

monocasa 6y ago
If anyone is interested why R15 is special cased here a bit, it's because R15 is the program counter and that extra cycle is the interlock where they'd otherwise have to put a delay slot.
- progval 6y ago
  Hmm, I didn't know about that. Then it would be 20 or something. (The special case I accounted for is because there's a bubble in the instruction pipeline if the next instruction uses the last register)

eximius 6y ago

Are instructions typically variable in the number of cycles it takes? If, as the article claims, pop is truly aliased to ldm, then I'd expect it to be very fast.

progval 6y ago
They are, this one takes from 2 to something like 20 cycles, depending on the number of registers, an whether the PC is one of them.
lxgr 6y ago
> Are instructions typically variable in the number of cycles it takes? Very much so, either due to memory latency or just inherent complexity. For example, a single division instruction can easily take the same time as ten adds.
- eximius 6y ago
  I meant variant for the same instruction. Is expect a divide to be slower than an add but I wasn't sure if a single instruction would have a range.
grandmczeb 6y ago
Yes, even in very simple architectures instructions often take different numbers of cycles.

pja 6y ago

Who cares? Feel that code density ! More seriously, yup: if you read the architecture manual this instruction can take a long time. It's also a pain for a OoO (not superscalar!) cpu to keep track of all the dependencies. It made complete sense back in the early 80s when the instruction set was designed, but like universal condition code dependent instruction execution it was dropped from ARM64 for good reasons.

monocasa 6y ago
Superscalar doesn't really matter here (just throw in an interlock), but out of order very much does.
- pja 6y ago
  True! I was (inappropriately) thinking of SS as a combination of both.
kevincox 6y ago
Why would it be harder for OoO to keep track of this than N mov/load instructions? It is just that the dependency tracker is working in instruction space? As mentioned before these were microcoded anyways so it may end up "compiling" down to N loads which should track just as well.
- alain94040 6y ago
  Imagine you hit a bus error on the last memory access of LDM. You already updated 15 registers, so now you need to undo all of that. If instead you had executed 16 separate LD instructions, all of them would have retired and update state by the time the last one gets the bus error. It’s all doable of course, but it means your OOO algorithm and physical implementation need to handle a lot more state in flight.
  - tsomctl 6y ago
    Why couldn't you just not undo it, and have it read/write twice? This wouldn't be a problem if you're accessing normal ram, like the prologue and epilogue of a function. Add a comment to the manual saying to not use this instruction when reading/writing hardware registers where accessing it changes state.

LIV2 6y ago

Less than 16 individual loads since you're skipping 15 opcode fetches