In case of compute purpoused FPGA designs you could just have pure LUTs and internal routing blocks, and for significant increase of speed and reducing power us

In case of compute purpoused FPGA designs you could just have pure LUTs and internal routing blocks, and for significant increase of speed and reducing power usage math blocks like multipliers or dividers would be a big improvement to pure FPGAs. And except programming and communication interface that would be all that AMD would need to introduce FPGA based compute solutions. > where is the RISC-V of the FPGA world? sounds like a challenge ;-)