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The 486 was pipelined but not superscalar. You could approach 1 instruction per clock cycle but you could never go over 1. --- 286: protected memory extensio
by hapless 16y ago
The 486 was pipelined but not superscalar. You could approach 1 instruction per clock cycle but you could never go over 1.
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286: protected memory extensions for x86
386: useful protected memory extensions for x86. (Hardly anything used 286 protected memory.)
486: first RISC-like pipelined x86
586: first superscalar x86
- shasta 16y agoYou're right. What I really meant was that instructions were processed 'in order'. An uncached memory access slowed things down a particular amount and there was no way to cover the latency with other instructions.
- hapless 16y agoThe figure I found suggested that a 486 averages ~0.8 instructions per clock running full-tilt. That seems impossible unless one hardly ever hits memory. I'm not 100% certain, but I think the pipelining would allow you to execute (some) register-only instructions in the x86 equivalent of a delay slot.
- shasta 16y agoAccording to the specs, the original 80486 could read or write 16 bits per clock. That's probably on a DX - on a DX2 it's probably 2 clocks. And that's with in order execution - the bus was running at the same frequency as the CPU.