I'm not so sure that's something which is really feasible from a design point of view. Everything involving instructions in the CPU is extremely performance cri

I'm not so sure that's something which is really feasible from a design point of view. Everything involving instructions in the CPU is extremely performance critical and cross-cutting, so designing an interface which allows custom instructions without utterly destroying performance seems like quite a feat. I've a feeling the memory interface is a much more natural place for any integration (this is how it works on any existing FPGA + CPU chips)