3 ms·
IIRC, the 486 was not pipelined, so you did't get 19 instructions, 4 of which could be memory instructions. You got 19 arithmetic instructions or 4 memory inst
by shasta 16y ago
IIRC, the 486 was not pipelined, so you did't get 19 instructions, 4 of which could be memory instructions. You got 19 arithmetic instructions or 4 memory instructions, or something in between (without checking your math, but as I recall, that's roughly right).
There are basically two inner loop types in a game like Doom - the wall loop and the floor loop. The wall loop renders a vertical strip of pixels on a wall and the floor loop renders a horizontal strip of floor. Each of these loops is actually rather trivial to write and just walks over the pixels reading an input texel, modulate by lighting, and then write out to the screen buffer. (Actually, Doom had transparent textures for some walls, so that's a third type of loop). The wall loop is slightly simpler because it can be an axis aligned walk through the input texture.
There really isn't very much room to optimize these loops. You can unroll them. You can play with how you do the adds and carrys and maybe shave off another instruction. For walls, you can organize your texture data so that vertical neighbors are consecutive in memory. You can be very choosy about your lighting function. The hard work was setting everything up for your inner loop.
- hapless 16y agoThe 486 was pipelined but not superscalar. You could approach 1 instruction per clock cycle but you could never go over 1. --- 286: protected memory extensions for x86 386: useful protected memory extensions for x86. (Hardly anything used 286 protected memory.) 486: first RISC-like pipelined x86 586: first superscalar x86
- shasta 16y agoYou're right. What I really meant was that instructions were processed 'in order'. An uncached memory access slowed things down a particular amount and there was no way to cover the latency with other instructions.
- hapless 16y agoThe figure I found suggested that a 486 averages ~0.8 instructions per clock running full-tilt. That seems impossible unless one hardly ever hits memory. I'm not 100% certain, but I think the pipelining would allow you to execute (some) register-only instructions in the x86 equivalent of a delay slot.
- shasta 16y agoAccording to the specs, the original 80486 could read or write 16 bits per clock. That's probably on a DX - on a DX2 it's probably 2 clocks. And that's with in order execution - the bus was running at the same frequency as the CPU.