4 ms·

> I bet a lot of design and architecture validation is done on big FPGAs. There was a talk at 32c3 (2015) by David Kaplan from AMD about developing and testing

> I bet a lot of design and architecture validation is done on big FPGAs. There was a talk at 32c3 (2015) by David Kaplan from AMD about developing and testing/verifying real world x86 CPU designs: https://media.ccc.de/v/32c3-7171-when_hardware_must_just_work https://media.ccc.de/v/32c3-7171-when_hardware_must_just_wor... Around minute ~11/12 he briefly mentions (among other methods) emulation on massive FPGA workstations costing something in the order of $1M.

tails4e 6y ago
Yep, emulation is huge. HAPS by Synoosys for example has a bunch of huge Xilinx FPGAs in there. I've never used one, but apparently it takes care of splitting the huge ASIC design over the array of FPGAs so it looks like a single chip, and can run at 100s of MHz, so way better than simulation that could be a few kHz at best