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I think this is a terrible idea for the future of technology. AMD would not be existentially dependent on the FPGA market and the stack is so important to cutti
by amirhirsch 6y ago
I think this is a terrible idea for the future of technology. AMD would not be existentially dependent on the FPGA market and the stack is so important to cutting-edge tech that it demands focused stewardship. It's clear something needs to change in FPGA land. Xilinx and Intel both produce abhorrent FPGA software causing project delays and cancellations of cutting-edge technology dependent on their devices. Xilinx probably needs an activist investor to force their software to move past the time in history when Java was something you put on your resume. Maybe AMD can be that, but I doubt it and an acquisition by AMD would likely result in the same abandonment we see from Intel towards Altera.
Xilinx had an opportunity to be in the position NVidia is in today and it was not obvious in 2005 who was going to win the high performance computing (HPC) market because the inherent advantages that FPGAs had and still have today for high speed I/O, RAM throughput, and hard timing requirements. NVidia's CUDA, on the other hand, produces generally painlessly portable results, with easy improvement on new devices. They have essentially won in HPC application development.
Fundamentally the FPGA companies need to adopt an open-source, cloud-first ethos towards their stacks and especially be focused on making agile low-level application development. Making a counter control some LEDs should be a 10 second process. Changing the clock speed should be a 1 seconds process. Adding a button to reset the counter should be a 1 second process. None of this is true. Good luck getting this to work within one day as a newbie on a vanilla machine. Good luck even installing Vivado and compiling any bitstream in one day (thank God they have AWS images -- good luck getting that going within 2 hours). Good luck coordinating with source control and generally merging work with a team.
There was some hope when Intel bought Altera that the compilers engineering expertise might help improve virtual CPU stacks, or at least some investment in the usability of their software tools might have been thought of as a competitive advantage, but all the FPGA vendors have seriously dropped the ball on improving the eco-system with usable software. FPGA software is so bad that you have to justify a 6 month development cycle for something that should probably take a few days if things were even remotely sane. It's hard to enumerate all the examples of broken-ness but small changes end up taking a long time to re-build, things like inverting your reset in a module and then waiting two hours for trivial changes to resynthesize and place-and-route. (edit, two hours later the trivial reset polarity inversion failed timing, because it also required me to add synchronization stages to send the inverted reset signal across clock domains, shouldn't be doing this at night).
- panpanna 6y agoAgreed, altera looks dead since intel took over. This is probably good news only for Lattice Semiconductor.
- derision 6y agoWhen Jim Anderson left AMD to take on CEO at Lattice I invested heavily in them with the thesis that there would be an eventually merger. Unsure what to do now
- panpanna 6y agoWith microsemi doing everything wrong, altera going invisible and xilinx soom to becomes AMDs toy project, who else should you invest in?
- bcrl 6y agoI'm curious what you mean about Microsemi doing everything wrong? I've been pretty happy with my experience with the Polarfire line so far.
- DoingIsLearning 6y ago> Xilinx and Intel both produce abhorrent FPGA software causing project delays and cancellations of cutting-edge technology dependent on their devices. I feel this pain!!!! Absolutely love the flexibility of Xilinx's System-On-Module architectures but their Software toolchain is arguably the most time-wasting frustrating piece of software I have ever had to work with. We need an open-source LLVM-like toolchain equivalent for FPGA's. I hope AMD has enough muscle to push for this. I would also like to point out that there are projects out there pushing this boundary, David Shah has made amazing contributions towards this, with projects like SymbiFlow and yosys.
- pjbk 6y agoTotally agree. Being involved with FPGAs for 20+ years now, and Xilinx for the most part of it, I have witnessed the progressive decay of their software quality. The legacy Xilinx tools (Foundation) were far from perfect but at least useable -- and hackable to a degree if you needed to implement workarounds. Those were many times even suggested by Xilinx own employees that were easy to approach and responsive back in the days. Altera Quartus was always better in terms of project organization and user interface, including their hardware tools. Third party software such as Synplify (before Synopsys bought their maker Synplicity) were light-years ahead, especially on the synthesis introspection and support for design and RTL troubleshooting. People tend to justify the software quality and vendor lock-in because these are niche markets. I think that is a lame statement. You could tell both Xilinx and Altera, being "fabless hardware companies", treated their software departments as a necessary burden and not a critical part of their business model, which by de facto it was. The software started going downhill, progressively accumulating technical debt while it kept getting even more cryptic and expensive. I think they offshored a significant part of its maintenance in the last decade. Each release fixed bugs but astonishingly introduced very stupid new ones that a minimally decent software verification process should have caught. Vivado is a mess. You can optimize your workflow digging down deeply with TCL scripts (yikes, its 2020!). However who has the time for learning their badly designed API and fighting with the quirkiness of their tools? I am amazed some of us use it in regulated environments where our tools need to be properly validated. I have had designs that take more than one day to synthesize, map and route. Having being bitten by some bugs and my own errors dealing with the cumbersome IDE, I always painfully go through all the logs of each step, and also many times recreate the project and rebuild just to check if the output is reproducible.