4 ms·

I think you'd have a hard time making a large FPGA actually part of a CPU die due to area. A peer on the memory bus ala CCIX on the other hand... Have you ever

by ip26 6y ago

I think you'd have a hard time making a large FPGA actually part of a CPU die due to area. A peer on the memory bus ala CCIX on the other hand... Have you ever thought of building your own processor or maybe just defining your own machine instructions? With eMIPS now you can. Microcode strikes me as the natural way to define arbitrary instructions.

rcxdude 6y ago
I'm not so sure that's something which is really feasible from a design point of view. Everything involving instructions in the CPU is extremely performance critical and cross-cutting, so designing an interface which allows custom instructions without utterly destroying performance seems like quite a feat. I've a feeling the memory interface is a much more natural place for any integration (this is how it works on any existing FPGA + CPU chips)