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They make this sound like a large change to the fundamental design of these chips. That gets me wondering: how do they test redesigns during development? I assu
by tgb 6y ago
They make this sound like a large change to the fundamental design of these chips. That gets me wondering: how do they test redesigns during development? I assume it's very hard to predict the performance impact of many changes. How often are they manufacturing test chips to measure performance? How much does that cost to do? Can you realistically simulate performance characteristics?
- wmf 6y agoIt's too expensive to fab test chips so it's all done using cycle-accurate simulation software like SimpleScalar or gem5 and later using FPGA-based emulation like Palladium/ZeBu.
- universal_sinc 6y agoThey way modern CPU design works is that the development team maintains a cycle-accurate software model of the CPU. Changes can be made to the pipeline and memory system, those changes simulated against a real workload, and results reported without ever laying a single transistor. These models are part of the secret sauce to figuring out how to eek out 19% IPC. Yes the simulations are slow. But you can get a lot of value out of 50k or 100k simulated clock cycles.
- vtail 6y agoYou can run emulations. When I was at NVIDIA almost 10 years ago, they were number 1 user of electricity in Santa Clara, by a big margin, because of their server farm that was used to emulate chips.
- coopierez 6y agoSimulations, not emulations!