4 ms·
> is still preferred because of better AVX support AVX1 and AVX2 performance is on par. For instance, vmulpd AVX1 instruction is faster on AMD, 3 versus 4 cyc
by Const-me 6y ago
> is still preferred because of better AVX support
AVX1 and AVX2 performance is on par.
For instance, vmulpd AVX1 instruction is faster on AMD, 3 versus 4 cycles. vpaddd AVX2 instruction is same at 1 cycle latency. vfmadd132pd FMA instruction is slightly faster on Intel, 4 versus 5 cycles. Throughput is the same across these two. I was looking at AMD Zen2 versus Intel Ice Lake.
Some Intel chips have AVX512. Still, many practical applications don’t need that amount of SIMD wideness, and these who do are often a good fit for GPGPUs.
> There are also things like Intel MKL
There’re vendor-agnostic equivalents like Eigen.
- f311a 6y agoFor some computer vision tasks, Tensorflow is much faster when you have AVX512. Also https://www.intel.com/content/www/us/en/artificial-intelligence/posts/tensorflow-optimizations-intel-xeon-scalable-processor.html https://www.intel.com/content/www/us/en/artificial-intellige...
- Const-me 6y agoThese results were achieved on dual-socket Xeon E5 2699v4 (the architecture is 5 years old and has no AVX512, they optimized for AVX2) and on Xeon Phi 7250 (that thing does have AVX512 but that’s not a processor, a specialized accelerator with 68 cores). Also Tensorflow is awesome fit for GPGPUs and is usually way faster on them.
- DoofusOfDeath 6y agoIIUC, Intel uses the term "AVX-512" as an umbrella term, and different processors support different subsets of "AVX-512" instructions [0]. AFAIK this is a break from previous Intel nomenclature, where any processor supporting e.g. "SSE4.2" instructions was guaranteed to support all SSE4.2 instructions. I'm concerned that sometimes this causes confusion when talking about processor -- software compatibility. [0] https://en.wikipedia.org/wiki/AVX-512 https://en.wikipedia.org/wiki/AVX-512
- loeg 6y agoI think the consideration GP was trying to make is that Zen (at least 1 and 2 — and I haven't heard otherwise for 3) do not support 512-bit wide AVX registers at all.
- singhrac 6y ago> There’re vendor-agnostic equivalents like Eigen. That's looking at the wrong layer of the hierarchy, I think. There are many open-source linear algebra libraries, but iirc they all link against something that has a BLAS/LAPACK API. That might be something like MKL, OpenBLAS, ATLAS, etc. When I last checked, MKL was much faster than its competitors, and is only available (at full speed) on Intel CPUs. Has that changed?
- Const-me 6y ago> iirc they all link against something that has a BLAS/LAPACK API Eigen can consume these I think, but they are optional. It has it’s own implementation of these, written in manually vectorized C++, with intrinsics, up to and including AVX512 (controlled with macros). For parallelization it uses OpenMP provided by the compiler (also controlled with a macro). > Has that changed? It’s hard to directly compare Eigen to the rest of them. They don’t do the same thing. One feature of Eigen is lazy evaluation. Expressions like a+b or a×b don’t return another matrix or vector; they return a placeholder object that only computes something on assignment. For complicated expressions this can be a huge win, e.g. r=a+b+c+d will read from a,b,c,d, compute sum of the 4 on the fly, and write into r without temporary copies in memory. However, also makes Eigen’s source code outright scary, and hard to debug or optimize. Anyway, based on the old pics there http://eigen.tuxfamily.org/index.php?title=Benchmark http://eigen.tuxfamily.org/index.php?title=Benchmark they are more or less comparable. Things like alpha·X+beta·Y were much faster in Eigen (probably due to that lazy evaluation thing), Hessenberg was much faster in MKL, in general they are close.
- gnufx 6y ago> When I last checked, MKL was much faster than its competitors That has never been generally true in my experience measuring over the years. It has been true at times for specific cases, e.g. OpenBLAS until it got avx512 support on a par with MKL (at least for serial DGEMM -- I've forgotten quite how the rest of level 3 goes).