4 ms·
> Using threads -especially low-level threads- can lead to a real education in debugging. Oh yeah it can. I'm still scarred by an error that took me a month t
by mmm_grayons 6y ago
> Using threads -especially low-level threads- can lead to a real education in debugging.
Oh yeah it can. I'm still scarred by an error that took me a month to solve: I was self-teaching pthreads and kept getting an access violation with a stack trace starting at 0x0.
- eloff 6y agoThe only bug that ever beat me in my two decades coding was in a custom lock free data structure using an early version of c++11. I spent a month on it, including writing custom visualization and logging tools, but I never found the issue that caused a crash once every few hundred billion operations. Later I saw some suspicious compiler bug fixes around compare and swap, and I still wonder if that was maybe it.
- blkhp19 6y ago1 in every hundred billion... is that low enough odds to be cosmic rays?
- saagarjha 6y agoA hundred billion operations is spinning on a loop for a couple minutes, so not really.
- eloff 6y agoIt took about ten minutes at full system utilization on all cores, running the "torture test" in a loop in each thread.
- saagarjha 6y agoFor a cosmic ray bit-flip, or to perform a hundred billion operations?
- eloff 6y agoOne hundred billion operations. The machine didn't have ECC memory, so a bit flip is a possible explanation. I should have checked if it was reproducible with ECC. I still think a logic bug or compiler bug was at fault though.
- infradig 6y agoObligatory sometimes, just sometimes, it is the compiler.
- Gibbon1 6y agoI read that some lock free libraries needed to be updated when Apple released it's first dual core ARM processors. Something about ARM's read or write ordering guarantees are looser than Intels. Me I'd rather roll my own cryto than try and write my own lock free data structure.
- saagarjha 6y agoFun fact: Apple's recent processors have a mode where they emulate stricter ordering guarantees (for Rosetta, of course).
- Gibbon1 6y agoThat reminds me I think I saw some blurb in an MCU data sheet that mentioned the processor can do out of order memory accesses which if you're an embedded guy tends to freak you out. However the chip designers disabled that for peripheral memory accesses. Which is very nice of them.
- DougBTX 6y agoYes, this is something where different CPU architectures do it differently, even between ARMv7 and ARMv8 etc. There's a great presentation on the differences here: https://channel9.msdn.com/Shows/Going+Deep/Cpp-and-Beyond-2012-Herb-Sutter-atomic-Weapons-1-of-2 https://channel9.msdn.com/Shows/Going+Deep/Cpp-and-Beyond-20... https://channel9.msdn.com/Shows/Going+Deep/Cpp-and-Beyond-2012-Herb-Sutter-atomic-Weapons-2-of-2 https://channel9.msdn.com/Shows/Going+Deep/Cpp-and-Beyond-20... He goes into the details of ARM vs Intel etc in the middle of part 2, but really part 1 is well worth a watch.