3 ms·
> Does the vdivps instruction set the division-by-zero flag? Yes. It even triggers a runtime exception when these are enabled in the corresponding bit of MXCSR
by Const-me 6y ago
> Does the vdivps instruction set the division-by-zero flag?
Yes. It even triggers a runtime exception when these are enabled in the corresponding bit of MXCSR status register.
> I don't think compiling code that doesn't divide by zero into code that does is correct.
There’re good arguments both for and against.
Personally, I think it’s fine. The optimization clang did almost doubled the performance. Most people don’t touch these bits in MXCSR, and the default values are good.
When manually vectorizing, I sometimes manually writing code like that when the alternatives are much slower. In this particular example it’s possible to fix for free by replacing vmovsd with vmovddup, _mm_loaddup_pd in C++. But it’s not always the case, e.g. when dealing with 3D vectors you need extra instructions.
In SSE the fastest way is _mm_insert_ps, it can either copy 3-rd lane into 4-th one, or selectively zero out lanes, a single very fast instructions that doesn't touch memory. In AVX however you would need memory access + _mm256_blend_ps.