3 ms·
I'm going off topic a bit here, but it's something I've thought of before... We're at the point where single-core performance gains on each generation are weak
by Sohcahtoa82 6y ago
I'm going off topic a bit here, but it's something I've thought of before...
We're at the point where single-core performance gains on each generation are weak, and instead are now heading for massive parallelization. Is the the speed of light (more specifically, the speed of current) actually the limiting factor here?
At 5 Ghz, in the time it takes for the clock to tick once, light travels 6 cm (2.36 inches). I know electrical current moves even slower than that (and varies depending on the material), so is it possible that it could impact theoretical maximum performance per core, at least limiting clock speeds, due to signals going across the CPU and across components being out of sync?
- bullen 6y agoSpeed of memory has been the bottleneck all along. More transistors are only useful if they are L1 cache, but to take advantage of larger caches we need to change the OS/languages we use. I would say 1 Gflops/Watt is peak 32-bit CPU, I think most people should try and work from that number and keep energy usage as low as possible. Raspberry 4 for desktop! 28nm is enough, going smaller creates more problems than it solves.
- qppo 6y agoWe can make memory 10x faster for 20x the price, but most devices barely need it at 0.5x the current speed so there's no demand to drag that price down.
- SAI_Peregrinus 6y agoSynchronizing clock domains is already an issue. More commonly a problem in FPGAs (larger dies, more buffering & switching, so slower clock traversal across a larger distance), but it definitely has to be accounted for in CPU design.