3 ms·
Technically it’s figured out. Gate-all-around has been experimentally demonstrated at pitches less than FinFET. The primary problem is, who is going to pay it.
by egsmi 6y ago
Technically it’s figured out. Gate-all-around has been experimentally demonstrated at pitches less than FinFET. The primary problem is, who is going to pay it. The economics are very tough at these 1s of nm nodes but hopefully that’s only a transitory problem.
- ksec 6y agoYou are talking about GAA at 2nm, I was talking about sub 1nm ( Node naming ) Tech. Which the OP was referring to "true" 7nm or Gate pitch / metal pitch at sub 7nm. We are still quite far away from figuring those out. But yes, I agree the economics model is tough as I have been stating on various forums for years. That is part of the reason why we see Semi-conductors consolidation, like Marvell, Broadcom. My best guess is that some time in 2026/ 28 we might have to stretch the cycle to three years instead of two. Giving more time to amortised those cost. But HyperScaler Cloud Market seems to be not limited by any R&D funding so I am actually quite optimistic we could see the current 2 year cadence all the way to 2030. Anything beyond is just too hard to predict or infer.