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But there is no box! RISC-V is just an ISA; ARM also requires you to write a lot of your own verification, unless you buy VIP (possibly even more expensive than
by denotational 6y ago
But there is no box! RISC-V is just an ISA; ARM also requires you to write a lot of your own verification, unless you buy VIP (possibly even more expensive than the architectural license) from Arm.
RISC-V does however have a complete formal specification, unlike other ISAs, which is absolutely not just a "black box reference design".
- ip26 6y agoI'm not claiming there should be, but this is a thing people tend to complain about. This is ultimately why the market for hard IP drop-in ARM cores flourished. A lot of the excitement I see around RISC-V seems to go like this: Wow, the RTL is open source! This is so great, anybody will be able to tape out their own custom core in like a week! People don't realize it's just a starting point, instead of a complete product.
- moring 6y agoAs long as you are talking about RISC-V itself and not about a specific implementation, the RTL is neither open source nor not open source because there is no RTL. RISC-V is an instruction set specification. As a CPU hobbyist, what this gives you is not a single step towards tapeout, but rather a working software-side toolchain (assembler, compiler, ...) right from the start, plus a sensible instruction set and encoding made by people who know what they are doing.