Status flags are a bit of a nightmare if you're building a massively superscalar implementation, every instruction has an explicit dependency on the one before

Status flags are a bit of a nightmare if you're building a massively superscalar implementation, every instruction has an explicit dependency on the one before - there have been a bunch of different solutions which often cost instruction decode space. RISC-V says "usually we don't care, let's only take the cost when we really need it" which is a very RISCish sort of thing to do. For those who haven't dabbled RISC-V has compare-and-branch instructions rather than branch on condition instructions