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> but that's not the point. Its 2020. We've known how RISC machine's evolve for 3 decades or so, yet RISC-V rewound the clock almost back to the beginning. "
by brandmeyer 6y ago
> but that's not the point.
Its 2020. We've known how RISC machine's evolve for 3 decades or so, yet RISC-V rewound the clock almost back to the beginning. "Let them eat extensions" is a recipe for fragmentation. MIPS actually experienced this in the field. ARM floating-point did for many years, too.
- andrekandre 6y ago> "Let them eat extensions" is a recipe for fragmentation. not neccessarily in machine mode (think firmware or hypervisor level) you can trap on unrecognized instructions and handle them retroactively in software), so maybe fragmentation wont be (at least technically) a big issue....
- brandmeyer 6y agoI remember the awful days of fake hard-float support in ARMv4. Trapping to the kernel and doing soft float there was was 10x worse than just doing soft float in userspace in the first place. Now, imagine doing that for xor-and-rotate, or bitfield insert/extract. Or leading zero count, or indexed memory access. No. Thanks.
- ncmncm 6y agoExactly. Emulation would be even worse than omission. Putting in optimizations that make the slowest hardware run even slower is not the route to happy users.