4 ms·

Essentially it wouldn't be RISC is there were more complex addressing modes (if you can't do it in one clock at speed .....)

msla 6y ago
Complex addressing modes are un-RISCy because they're harder to pipeline: Memory accesses might result in page faults, and if you have complicated addressing modes, all of a sudden you have some nontrivial ALU state to back out before you can handle the fault. It's a lot simpler to have rock-dumb load/store opcodes and then do all ALU work in terms of register-register opcodes which don't touch memory. John Mashey (helped design the MIPS architecture) has a great account of how complex addressing modes are difficult to work with partway down this page: https://userpages.umbc.edu/~vijay/mashey.on.risc.html https://userpages.umbc.edu/~vijay/mashey.on.risc.html I can't link to it directly, but it starts with this text: > General comment: this may sound weird, but in the long term, it might be easier to deal with a really complicated bunch of instruction formats, than with a complex set of addressing modes, because at least the former is more amenable to pre-decoding into a cache of decoded instructions that can be pipelined reasonably, whereas the pipeline on the latter can get very tricky (examples to follow). This can lead to the funny effect that a relatively "clean", orthogonal archiecture may actually be harder to make run fast than one that is less clean. Obviously, every weirdness has it's penalties.... But consider the fundamental difficulty of pipelining something like (on a VAX): ADDL @(R1)+,@(R1)+,@(R2)+ > (I.e., something that, might theoretically arise from: register **r1, **r2; **r2++ = **r1++ + **r1++; ... and he then goes on a detailed step-by-step process of what has to happen to execute that opcode in the world of page faults and unaligned memory accesses, another thing classic RISC chips were very down on, but I think they've gotten a bit looser on them in recent decades.
- devit 6y ago
  This only applies to addressing modes with side effects, which e.g. x86 doesn't have.
  - Taniwha 6y ago
    well except for push/pop, and all the microcoded stuff. IMHO the x86 has been successful because it started out semi-RISCy - no indirect addressing modes, no auto inc/dec, only one memory access per instruction - (except for push/pop and the microcoded segment stuff). It means either an instruction goes to completion, or it faults, there's no state change to undo if something takes a TLB miss - compared with a 68k etc it's an easy implementation
  - ordu 6y ago
    rep movsb

msla 6y ago

Complex addressing modes are un-RISCy because they're harder to pipeline: Memory accesses might result in page faults, and if you have complicated addressing modes, all of a sudden you have some nontrivial ALU state to back out before you can handle the fault. It's a lot simpler to have rock-dumb load/store opcodes and then do all ALU work in terms of register-register opcodes which don't touch memory. John Mashey (helped design the MIPS architecture) has a great account of how complex addressing modes are difficult to work with partway down this page: https://userpages.umbc.edu/~vijay/mashey.on.risc.html https://userpages.umbc.edu/~vijay/mashey.on.risc.html I can't link to it directly, but it starts with this text: > General comment: this may sound weird, but in the long term, it might be easier to deal with a really complicated bunch of instruction formats, than with a complex set of addressing modes, because at least the former is more amenable to pre-decoding into a cache of decoded instructions that can be pipelined reasonably, whereas the pipeline on the latter can get very tricky (examples to follow). This can lead to the funny effect that a relatively "clean", orthogonal archiecture may actually be harder to make run fast than one that is less clean. Obviously, every weirdness has it's penalties.... But consider the fundamental difficulty of pipelining something like (on a VAX): ADDL @(R1)+,@(R1)+,@(R2)+ > (I.e., something that, might theoretically arise from: register **r1, **r2; **r2++ = **r1++ + **r1++; ... and he then goes on a detailed step-by-step process of what has to happen to execute that opcode in the world of page faults and unaligned memory accesses, another thing classic RISC chips were very down on, but I think they've gotten a bit looser on them in recent decades.

devit 6y ago
This only applies to addressing modes with side effects, which e.g. x86 doesn't have.
- Taniwha 6y ago
  well except for push/pop, and all the microcoded stuff. IMHO the x86 has been successful because it started out semi-RISCy - no indirect addressing modes, no auto inc/dec, only one memory access per instruction - (except for push/pop and the microcoded segment stuff). It means either an instruction goes to completion, or it faults, there's no state change to undo if something takes a TLB miss - compared with a 68k etc it's an easy implementation
- ordu 6y ago
  rep movsb