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> we just came to accept that 100% of RAM is defective by design. Computing itself is broken. Every product from physical to application state is broken in som
by WrtCdEvrydy 6y ago
> we just came to accept that 100% of RAM is defective by design.
Computing itself is broken. Every product from physical to application state is broken in some subtle way which is then countered by a higher layer having some extra code (or component) to adjust it.
- myself248 6y agoBut it happens, or it becomes "accepted", at a certain level of complexity. When you're down at the Ben Eater or Gigatron scale, you can prove with simple logic and timing diagrams that every possible machine state is correct. Somewhere in the quest for higher speeds, RAM runs with timings and refresh intervals that allow rowhammer. And since nobody wants to take the speed hit of having memory that's actually correct, it just.... it's okay now? Well, I disagree. I'd like to find out how to configure my memory controller to be rowhammer-proof, even if that means a refresh cycle after every single access cycle. And then we can build performance starting from that assumption that correctness is required. As an old mentor once said, if you start out medium-speed but wrong, you'll get faster at doing it wrong. Start slow but right, and then you get faster at doing it right.
- WrtCdEvrydy 6y ago> And since nobody wants to take the speed hit of having memory that's actually correct, it just.... it's okay now? Yeah, same thing with Spectre... part of the ToS actually states you can't benchmark Intel products with Spectre mitigations applied now (apparently that's a thing)