3 ms·
How would this actually work? Memory access on your non-ecc processor is (for example) 64 bits wide. Your data is using all 64 bits. Perhaps you would only use
by Thetawaves 6y ago
How would this actually work?
Memory access on your non-ecc processor is (for example) 64 bits wide. Your data is using all 64 bits. Perhaps you would only use 56 bits for user data and 8 bits of ecc data on every read? Suddenly you need two memory accesses to read your 64bit value?
- stormbrew 6y agoI suppose you could have an extra dimm slot just for ecc storage, and only require it to be 1/8 the size of total ram on the normal slots. (I think there are probably issues with this in terms of how ddr itself actually works with its interleaving and adding a third channel to access from but I don't know enough about how it works to know for sure if that's the case)
- jasonwatkinspdx 6y agoSeparate channels are not timing locked. This would involve a lot more complexity and cost than the current practice. At the end of the day, electrical/computer engineers do actually generally know what they're doing.