3 ms·

Needing an additional bit to store ECC data is not a technical problem?

• theginger 6y ago
  The point he is trying to make is you don't need additional bits, you just need bits, they could be additional, or they could be subtracted from what is available.
  • Thetawaves 6y ago
    How would this actually work? Memory access on your non-ecc processor is (for example) 64 bits wide. Your data is using all 64 bits. Perhaps you would only use 56 bits for user data and 8 bits of ecc data on every read? Suddenly you need two memory accesses to read your 64bit value?
    • stormbrew 6y ago
      I suppose you could have an extra dimm slot just for ecc storage, and only require it to be 1/8 the size of total ram on the normal slots. (I think there are probably issues with this in terms of how ddr itself actually works with its interleaving and adding a third channel to access from but I don't know enough about how it works to know for sure if that's the case)
      • jasonwatkinspdx 6y ago
        Separate channels are not timing locked. This would involve a lot more complexity and cost than the current practice. At the end of the day, electrical/computer engineers do actually generally know what they're doing.
• bcrl 6y ago
  Speed does not decrease with ECC memory -- you might be thinking of the extra cycle of latency associated with registered memory, and that's hardly a 100% penalty. Unbuffered ECC DIMMs have no penalty compared to non-ECC DIMMs. Shipping 72 bits to the CPU instead of 64 bits costs a bit more power, nothing more. Your desktop CPU already has all the transistors needed to handle ECC memory, they're just disabled in consumer SKUs.