I’ve worked with systems which did this with two processors talking over SPI. The difficulty with integrating the real-time processor via shared memory is ensur

I’ve worked with systems which did this with two processors talking over SPI. The difficulty with integrating the real-time processor via shared memory is ensuring the real time processor has exclusive memory access to the peripherals it’s using. The control registers might be helpful here provided the bootloader can be trusted to configure them and the rest of the OS kernel doesn’t mess with them at startup. The client PRU is entirely at the mercy of the main OS. So it’s hard to argue that you have perfect separation here like you can when you have separate chips talking over a bus. You may also run out of pins to mux peripherals through as display functions and IO can take a lot of pins.