I think it was just a matter of evolutionary steps. The P5 had two 32bit ALU pipes, and a bank of 64bit registers for the FPU, so MMX was a relatively modest ex

I think it was just a matter of evolutionary steps. The P5 had two 32bit ALU pipes, and a bank of 64bit registers for the FPU, so MMX was a relatively modest extension attop them to support 64bit wide short vector SIMD. SSE switched to using dedicated registers and wider widths, but was an evolutionary improvement. I'm pretty curious whether Arm SVE, or the similar design in RISC-V, will pressure x86 into a similar extension. The vector length agnostic binary support is certainly compelling.