Agreed, however there is a caveat. One of the things we discovered at NetApp doing performance analysis of Intel vs AMD designs (during the early Opteron days)

Agreed, however there is a caveat. One of the things we discovered at NetApp doing performance analysis of Intel vs AMD designs (during the early Opteron days) is that Intel's memory bandwidth was constrained by the transaction rate of their memory controller. Between pre-fetch traffic and pointer jumping workloads (which cause frequent TLB invalidation) they were never able to actually reach their theoretical bandwidth even with static ram instead of DRAM on the memory bus.