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The new Tiger Lake stills falls down against the competition when we start discussing raw throughput tests. Intel was keen to promote professional workflows wit

The new Tiger Lake stills falls down against the competition when we start discussing raw throughput tests. Intel was keen to promote professional workflows with Tiger Lake, or gaming workflows such as streaming, particularly at 28 W rather than at 15 W. Despite this we can easily see that the 15 W Renoir options with eight cores can blow past Tiger Lake in a like-for-like scenario in our rendering tests and our scalable workloads. The only times Intel scores a win is due to accelerator support (AVX-512, DP4a, DL Boost). On top of that, Renoir laptops in the market are likely to be in a cheaper price bracket than what Intel seems to be targeting. As I read this, and other reviews/analysis of the Tiger Lake node I can see Intel competing with the only tool it has left, specialized instruction sets. This continues to create a gap between things built for "i86-64" architecture vs "x86-64" architectures. What I expect to see from that is Intel touting performance advantages in applications that I don't use, and never comparing the performance of applications I do use. This is a bad place for Intel to be, but it is kind of like sailboat racing. In sailboat racing one boat can appear to be ahead of its rival to non-sailors, but sailors who know the boat is going to have to tack to make the mark recognize it is actually behind. So much of technology is like this, where the choices today ripple through the opportunities and choices you will have in the future, trying to guess which are the important ones feels more like divination than decision making. This is the second time AMD has made some good decisions that have resulted in an advantage. AMD's challenge has been to make these sorts of decisions on a regular enough cadence to maintain that advantage. If I were a leader in the CPU architecture or the manufacturing processes group at AMD I would be soooo stressed these days.

LargoLasskhyfv 6y ago
Here is some more divination stuff: https://www.tomshardware.com/features/intel-11th-gen-tiger-lake-superfin-10nm-benchmarks https://www.tomshardware.com/features/intel-11th-gen-tiger-l... which I've found to be more informative regarding the memory- and the bus-bandwith. tl;dr would be it has about 50% more peak memory bandwith than the best Renoir from AMD, which translates to about one third when all its cores use that. And can dynamically downclock the ring-bus and memory-interface while the cores are running at full speed. Which depending on the task can be good or bad for the task, but always good for battery. While AMD is still on top of that when all cores are used, because it has twice many of them. edit: Some other report mentioned almost instaneous resume, and never more than 8 seconds boot time from cold start to running desktop.
- jeffbee 6y ago
  Ars Technica has a video of the Intel system going from a dead stop to Windows desktop in 7 seconds, but I trust Intel to get this right (look at the way a NUC boots) and I absolutely do not trust any laptop maker to follow their example.
- ChuckMcM 6y ago
  Agreed, however there is a caveat. One of the things we discovered at NetApp doing performance analysis of Intel vs AMD designs (during the early Opteron days) is that Intel's memory bandwidth was constrained by the transaction rate of their memory controller. Between pre-fetch traffic and pointer jumping workloads (which cause frequent TLB invalidation) they were never able to actually reach their theoretical bandwidth even with static ram instead of DRAM on the memory bus.
glangdale 6y ago
The treatment of AVX-512 as some sort of weird benchmarketing trick is probably well deserved (given Intel's misfires in this area) but I'm not sure it's 100% reasonable. Anything that can be sped up with AVX2 can likely be further sped up with AVX-512, and some aspects of the ABI make it more likely that AVX-512 (especially in its ICL/TGL flavor) will be able to be more broadly applicable. Notably, masked operations and a reasonable scatter/gather implementation make it more likely that an algorithm can be rewritten as SIMD. The clock license penalties with AVX-512 are also mitigated on ICL/TGL. Don't get me wrong: I still think it's an uphill battle for Intel to get broader acceptance for AVX-512 (and they are their own worst enemy with many decisions, like fusing off everything beyond SSE4.2 on Celeron/Pentium branded products), and some (not all) of the workloads that are nice on AVX-512 are also pretty nice on GPGPU.

LargoLasskhyfv 6y ago

Here is some more divination stuff: https://www.tomshardware.com/features/intel-11th-gen-tiger-lake-superfin-10nm-benchmarks https://www.tomshardware.com/features/intel-11th-gen-tiger-l... which I've found to be more informative regarding the memory- and the bus-bandwith. tl;dr would be it has about 50% more peak memory bandwith than the best Renoir from AMD, which translates to about one third when all its cores use that. And can dynamically downclock the ring-bus and memory-interface while the cores are running at full speed. Which depending on the task can be good or bad for the task, but always good for battery. While AMD is still on top of that when all cores are used, because it has twice many of them. edit: Some other report mentioned almost instaneous resume, and never more than 8 seconds boot time from cold start to running desktop.

jeffbee 6y ago
Ars Technica has a video of the Intel system going from a dead stop to Windows desktop in 7 seconds, but I trust Intel to get this right (look at the way a NUC boots) and I absolutely do not trust any laptop maker to follow their example.
ChuckMcM 6y ago
Agreed, however there is a caveat. One of the things we discovered at NetApp doing performance analysis of Intel vs AMD designs (during the early Opteron days) is that Intel's memory bandwidth was constrained by the transaction rate of their memory controller. Between pre-fetch traffic and pointer jumping workloads (which cause frequent TLB invalidation) they were never able to actually reach their theoretical bandwidth even with static ram instead of DRAM on the memory bus.

glangdale 6y ago

The treatment of AVX-512 as some sort of weird benchmarketing trick is probably well deserved (given Intel's misfires in this area) but I'm not sure it's 100% reasonable. Anything that can be sped up with AVX2 can likely be further sped up with AVX-512, and some aspects of the ABI make it more likely that AVX-512 (especially in its ICL/TGL flavor) will be able to be more broadly applicable. Notably, masked operations and a reasonable scatter/gather implementation make it more likely that an algorithm can be rewritten as SIMD. The clock license penalties with AVX-512 are also mitigated on ICL/TGL. Don't get me wrong: I still think it's an uphill battle for Intel to get broader acceptance for AVX-512 (and they are their own worst enemy with many decisions, like fusing off everything beyond SSE4.2 on Celeron/Pentium branded products), and some (not all) of the workloads that are nice on AVX-512 are also pretty nice on GPGPU.